Floating-point Mathematics IP Cores

Zipcores Floating-point Mathematics IP Cores are provided as native VHDL source code and are compatible with a wide range of FPGA, SoC, and ASIC technologies. ZipCores Floating-point IPs are compatible with standard IEEE 754 arithmetic. The Floating-point portfolio includes cores for all common floating-point operations, including multiply, divide, add/subtract, square-root, and conversion between floating-point formats. All the IPs are fully pipelined with very low latency. Floating-point Mathematics IP Cores are ideal for high-speed, high-throughput mathematical operations.