SN74HCS264DR

SN74HCS264/SN74HCS264-Q1 Shift Registers

Texas Instruments SN74HCS264/SN74HCS264-Q1 8-Bit Parallel-Out Shift Registers contain an 8-bit shift register with AND-gated serial inputs and an asynchronous clear (CLR) input. Data at the serial inputs can be changed while CLK is high or low, provided the minimum setup time requirements are met. All inputs include Schmitt-trigger architecture, which adds noise margin and eliminates any input transition rate requirement. Clocking occurs on the low-to-high-level transition of CLK. Upon a clock trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The outputs are inverted from the data stored. The Texas Instruments SN74HCS264-Q1 devices are AEC-Q100 qualified for automotive applications.