Bench Talk

Modern Autonomous Robots Bring Sensing, Computing, and Movement Together

Tue, 30 Jun 2026 18:57:08 GMT

(Source: TechArtTrends/stock.adobe.com; generated with AI)

Robots are taking on roles with increasing levels of autonomy as their use proliferates in industrial, warehousing, and manufacturing applications. Consequently, designing these robotics systems requires expertise across multiple domains, from machine vision and sensing to embedded computing and motor control. As autonomy increases, so does the need for systems that can interpret and respond to real‑time conditions with speed and precision.

At their core, autonomous robots are full-stack systems made up of tightly integrated subsystems that work together seamlessly. To achieve optimal performance, hardware and software components must continuously exchange data, coordinate actions across all subsystems, and act on real-time information. To simplify this complexity, engineers often rely on a layered solutions stack that brings together hardware, software, and intellectual property (IP) blocks to streamline development of autonomous robots, drones, or industrial automation systems.

An effective solutions stack can ensure that data flows freely throughout the three core layers of autonomous robot designs: sensing via the perception layer, computing in the intelligence layer, and movement through the control layer. The three core layers, in turn, leverage cross-layer functions such as power management, communications, the human-machine interface (HMI), functional safety, and cybersecurity. This blog examines how autonomous robots integrate sensing, computing, and motion control through a layered solutions stack, and how this approach helps engineers manage complexity while enabling real-time, coordinated operation.

Building Situational Awareness Through Sensors

When it comes to autonomy, the sensing layer enables a robot to see the world it inhabits and build a model of its work environment. A robot performs simultaneous localization and mapping (SLAM) to build a map of its surroundings and identify its location within the mapped space.

Robots can employ a variety of sensing tools, each with advantages and disadvantages. Vision sensors, or cameras, for example, can capture high-resolution images and enable the robot to perform object recognition. However, adverse lighting and weather conditions can degrade vision sensors’ performance. Light detection and ranging (LiDAR) enables detailed 3D mapping but can be expensive and, like vision systems, can be considerably affected by weather conditions. Radar is often more robust than vision and LiDAR in poor weather or low-visibility conditions. Additionally, radar can measure a target’s distance and relative velocity using time-of-flight (ToF) and Doppler calculations, but it typically offers lower resolution than LiDAR and vision sensors. Ultrasonic sensors offer a cost-effective approach to collision avoidance, yet their range is limited.

Robots can also include inertial measurement units (IMUs) to augment other sensor modalities and measure angular velocity. In addition, a robot may include a Global Positioning System (GPS) receiver to augment position awareness, especially in large-scale outdoor applications such as agriculture.

An advanced autonomous robot will often employ sensor fusion, relying on the outputs of various sensor types to optimize accuracy and reliability. However, sensor fusion also places more demand on the robot’s computing section to process the various sensor inputs and make appropriate decisions.

Turning Sensor Data into Decisions

Data from the sensor layer flows to the computing layer, which performs planning and task selection, navigation and obstacle avoidance, and learning and adaptation based on that sensor data. A microcontroller unit (MCU) can be applied at this layer, and in fact, autonomous robot systems often use a mix of MCUs and other computing hardware for processing, depending on latency, functional safety, workload type, and cost. Traditional MCUs perform sequential computations and may not provide sufficient speed for handling safety-critical decisions in applications with sensor fusion.

In advanced robotics applications with high sensor bandwidth, strict timing requirements, or deterministic multi-stream processing, a field-programmable gate array (FPGA) can complement or, in some cases, replace a traditional MCU-based approach. FPGAs, whose hardware is programmable after shipment, can simultaneously process multiple sensor inputs while also controlling multiple axes of movement. To simplify a design task and speed time-to-market, engineers can choose an FPGA family with a robust portfolio of IP blocks. For robotics and vision designs, engineers often look for FPGA platforms with support for camera and sensor interfaces, such as Mobile Industry Processor Interface (MIPI) D-PHY/CSI-2, GigE Vision, USB3 Vision, Camera Link, or CoaXPress. Engineers might also opt for industrial and embedded interfaces, such as inter-integrated circuit (I2C), universal asynchronous receiver/transmitter (UART), analog-to-digital and digital-to-analog conversion (ADC/DAC), low-voltage differential signaling (LVDS), Ethernet, EtherCAT, and controller area network (CAN). The exact mix of native IP, partner IP, and reference-design support varies by vendor and platform.

Finally, an FPGA vendor may offer a variety of reference designs that can help engineers get started on robotics projects, while also offering development software and boards (Figure 1) that assist engineers with designing and evaluating their projects before implementing their own custom hardware.

Figure 1: A development board can help engineers start an FPGA design before building their own hardware. (Source: Altera)

Converting Decisions into Physical Action

The movement layer takes action based on decisions made in the computing layer, converting electrical power into movement. Based on instructions from the computing layer, this layer controls the application of power to actuators such as drive wheels, propellers, or the motors that rotate joints or extend limbs.

In addition to actuators, the movement layer includes the power-conversion stages that convert an autonomous robot’s battery power into the precise voltage and current profiles required for each actuator to perform its programmed task, whether that be traversing a factory floor or grasping a workpiece and relocating it. The entire movement layer must be optimized for efficiency, particularly for battery-powered robots, and it must be optimized for safety, with interrupt capabilities to avoid collisions.

The movement layer can include its own sensors—including IMUs for stability feedback, encoders for tracking actuator rotations, and force transducers for verifying proper grip strength. The compute layer uses all this feedback to close the control loop, continuously regulating each actuator and fine-tuning its commands to correct any discrepancies.

Using an FPGA in the compute layer can facilitate movement-layer design. The FPGA can simulate a motor and motor drive, allowing engineers to evaluate their designs before building physical power stages. This drive-on-chip capability supports fine-tuning designs for compliance with functional-safety requirements defined by the Safety Integrity Levels (SILs) specified in the International Electrotechnical Commission (IEC) 61508 standard for the functional safety of electrical, electronic, and programmable electronic systems.^[1]

Accelerating Development with a Robotics Solutions Stack

To facilitate the design of all robotic layers, Altera offers a Robotics Solutions Stack. The stack supports key applications ranging from industrial communications to motor control (Figure 2).

Figure 2: The Altera Robotics Solutions Stack extends from application support to development tools. (Source: Mouser Electronics)

The stack offers reference designs, including a Robot Operating System (ROS) consolidated robot controller and a motor drive-on-chip implementation that helps investigate functional-safety requirements in accordance with the IEC 61508 SIL2 standard. The stack also includes an IP ecosystem that supports a variety of functions, including network and vision interfaces and quadrature encoders. To help get projects started, Altera offers a suite of software development tools as well as development kits and boards in formats including FPGA Mezzanine Card (FMC) and Peripheral Component Interconnect Express (PCIe).

A complete solutions stack is important for building advanced autonomous robots, drones, or industrial automation systems. With Altera’s Robotics Solutions Stack, engineers are equipped with reference designs, IP, and development support for applications ranging from image processing to motor control.

Conclusion

Designing autonomous robots depends on tightly integrating sensing, computing, and actuation into a cohesive, layered system capable of responding to real-time conditions with speed and precision. Situational awareness encompasses diverse sensor inputs and sensor fusion, how meaningful decisions are formed through high-performance compute platforms such as FPGAs, and how those decisions are translated into precise, efficient physical actions through the control and movement layer.

Equally important is the role of a unified robotics solutions stack in reducing design complexity and accelerating development. A well-structured stack enables engineers to move more quickly from concept to deployment while maintaining performance and functional safety requirements.

[1] https://assets.iec.ch/public/acos/IEC%2061508%20&%20Functional%20Safety-2022.pdf?2023040501

How FPGAs Enable Efficient Edge AI

Thu, 21 Aug 2025 22:03:36 GMT

Cost-optimized FPGAs Accelerate AI with Configurable Logic

(Source: Leo Rohmann/stock.adobe.com; generated with AI)

In many applications, artificial intelligence (AI) processing at the edge offers the dual benefits of low latency for real-time tasks, such as industrial inspection, and enhanced security where data may be sensitive, such as in medical imaging. Central processing units (CPUs) and graphics processing units (GPUs) can handle many AI tasks, but edge devices have tight power, space, and cost budgets and need deterministic results. The inconsistent timing of CPUs and GPUs can cause issues in applications that require guaranteed, real-time responses.

Field-programmable gate arrays (FPGAs), on the other hand, deliver a flexible logic architecture that can be configured to run AI algorithms as logic circuits rather than as software routines.^[1] Since FPGAs run AI models as custom logic circuits, they use power more efficiently than CPUs or GPUs, making them a strong choice for deploying trained AI models at the edge. In this blog, we look further into the advantages FPGAs offer and examine design solutions for these integrated circuits.

Why FPGAs Beat CPUs and GPUs at the Edge

When quick decisions are needed, AI processing speed becomes crucial. Because FPGAs can be configured with logic pathways tailored to specific workloads, they provide the repeatable and predictable processing latency needed for high-speed and real-time applications.^[2]

Another advantage of FPGAs in edge AI systems is their input-output (I/O) flexibility. Their reconfigurable logic supports both high-speed data interfacing from a CPU and direct sensor-to-FPGA connections. In systems with multiple sensors and cameras, this can significantly offload CPU resources while also reducing latency during FPGA-based AI inferencing.

FPGAs are best suited for fast-moving applications where requirements are changing too quickly for an application-specific integrated circuit (ASIC) to make sense or in applications where the volumes don’t commercially justify ASIC development. The flexibility of the FPGAs also allows for the AI models to be updated as needs and advancements allow. In these instances, their reconfigurability helps engineers who need to tweak performance as the project evolves.

Design Considerations for FPGA-Based AI Systems

A common approach when using FPGAs for edge AI is to employ them as accelerators for host CPUs. In this architecture, the host processor offloads specialized AI tasks to the FPGA, which executes them more efficiently to enhance overall system performance. Alternatively, FPGAs can serve as standalone processors if their built-in CPU resources are sufficient.

One of the biggest challenges when running AI workloads on FPGAs is balancing model size and accuracy with hardware constraints such as memory and computing power. If a model is too small, it can miss important features, but if it's too large, it won't run efficiently on the device. To address this, developers use optimization techniques that reduce model complexity while maintaining acceptable performance. Some of these techniques include:

Weight sharing: Reduces the number of parameters by letting similar neurons use the same weights, helping the model recognize features, even if they shift position.^[3]
Model pruning: Eliminates parameters with minimal impact, reducing model size and computational overhead.^[4]
Quantization: Converts model weights to lower-precision data types (e.g., 32-bit floating point to 8-bit integer), decreasing memory usage and improving processing speed.^[5]

After optimization, the model is transferred onto the FPGA's logic units using dedicated software. The resulting implementation can then be tested to confirm it meets accuracy and performance targets.

Software Designed to Simplify AI Deployment on FPGAs

A common question that comes up is “How do I add AI to my FPGA?” Most FPGA developers have limited familiarity with working with AI, and the same is generally true for many AI developers and FPGA knowledge. A simplified way to integrate AI onto FPGAs is to develop the AI portion as an Intellectual Property (IP) block that can be instantiated in the FPGA in the same way as any other IP block, a natural way for FPGA developers to combine larger systems within the FPGA. This allows both developers to be experts in their own roles but easily work together to integrate AI compute on FPGAs.

The FPGA AI Suite from Altera helps solve the problem of converting the AI model to IP. It allows AI developers to work with models using their existing frameworks like PyTorch and meet target performance with minimal code changes. The model is optimized through OpenVINO and FPGA AI Suite which generates the IP. By connecting the IP and a host processing system, the FPGA team can easily integrate the inference IP and runtime together and deploy AI inference on Altera FPGAs faster.

FPGAs Designed for Edge AI Applications

For engineers looking to integrate a compact FPGA in edge AI applications, the Agilex^™ 3 family from Altera provides a high-performance, cost-optimized solution. Compared to earlier cost-optimized Altera devices, Agilex 3 FPGAs offer up to 38 percent lower power consumption along with several enhancements that support AI workloads at the edge:

2^nd Gen. HyperFlex core fabric: Enhanced FPGA fabric delivers faster, more efficient processing through the use of registers distributed throughout the routing fabric. Reduced bus widths help shrink package size, enabling more functionality in compact designs.^[6]
Power-efficient I/O: Advanced connectivity supports direct sensor-to-FPGA interfacing for lower-latency AI processing. As shown in Figure 1, available interfaces include true differential signaling (TDS), MIPI D-PHY, PCIe 3.0, 10GbE Ethernet, and LPDDR4.
Built for AI: The logic fabric includes AI tensor blocks and advanced digital signal processing (DSP) capabilities to support high-performance AI inferencing. This integration brings a tight coupling between the logic fabric and the AI capabilities, reducing the time and latency in the AI system. Using the tensor mode for AI enables 20 INT8 operations per clock cycle, a 5x improvement over previous DSP block architectures.
Optimal memory hierarchy: Agilex 3 FPGAs offer a memory hierarchy well suited for AI applications including: small MLAB memory and larger M20K block RAM connected to the AI tensor blocks for storing model weights and compute results. In addition, hardened LPDDR4 controllers allow simplified interfacing to larger off chip data buffers.
Integrated processor: A built-in dual Arm Cortex-A55 processor allows the FPGA to operate as a standalone AI processing unit in many applications, eliminating the need for a host CPU.

Figure 1: Block diagram of the Agilex 3 FPGA, illustrating its interface options. (Source: Altera)

With a built-in security module, the Agilex series is well suited for developers targeting data-sensitive edge AI applications such as industrial surveillance, consumer electronics, and medical imaging.

Getting Started with Agilex 3 FPGAs

For engineers evaluating the AI capabilities of Agilex 3 FPGAs, the C-Series Development Kit (Figure 2) supports rapid prototyping and application development, with an optional daughter card that adds PCIe connectivity for expanded interface support.

The kit offers a variety of I/O options and hardware resources for rapid prototyping, including:

Two DisplayPort 1.4 connectors supporting up to 8K video,
Two MIPI connectors for interfacing with mobile device cameras and displays,
One Pmod connector and one Raspberry Pi HAT connector for common development peripherals, and
Two LPDDR4 2GB memory modules for efficient performance.
Optional expansion card supporting PCIe 3.0 x1

Figure 2: Agilex 3 FPGA C-Series Development Kit offers a variety of I/O options to support rapid prototyping and application development of trained AI models at the edge. (Source: Altera)

FPGAs Expand the Possibilities for Edge AI

Edge devices are often limited by power and performance, but FPGAs tackle this challenge by running AI models as hardware logic instead of software. By doing this, they deliver deterministic and efficient performance that CPUs and GPUs cannot always match.

Altera has incorporated FPGA fabric infused with AI tensor blocks and advanced built-in features into the Agilex 3 family so the platform can handle AI tasks independently, without depending on a host processor. In addition, FPGA AI Suite from Altera greatly simplifies implementing AI algorithms on FPGAs. As AI finds its way into every part of technology, these kinds of improvements make FPGAs an increasingly important piece of edge computing.

Author

Brandon Lewis has been a deep tech journalist, storyteller, and technical writer for more than a decade, covering software startups, semiconductor giants, and everything in between. His focus areas include embedded processors, hardware, software, and tools as they relate to electronic system integration, IoT/industry 4.0 deployments, and edge AI use cases. He is also an accomplished podcaster, YouTuber, event moderator, and conference presenter, and has held roles as editor-in-chief and technology editor at various electronics engineering trade publications.

[1] https://qbaylogic.com/fpga/
[2] https://www.velvetech.com/blog/fpga-in-high-frequency-trading/
[3] https://www.kaggle.com/code/residentmario/notes-on-weight-sharing
[4] https://datature.io/blog/a-comprehensive-guide-to-neural-network-model-pruning
[5] https://huggingface.co/docs/optimum/en/concept_guides/quantization
[6] https://www.mouser.com/pdfDocs/agilex-3-fpgas-socs-product-brief.pdf