TMS320VC5510AZAVA1

Texas Instruments
595-S320VC5510AZAVA1
TMS320VC5510AZAVA1

Mfr.:

Description:
Digital Signal Processors & Controllers - DSP, DSC Fixed-Point Digital Signal Processors 24

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In Stock: 493

Stock:
493 Can Dispatch Immediately
Factory Lead Time:
18 Weeks Estimated factory production time for quantities greater than shown.
Quantities greater than 493 will be subject to minimum order requirements.
Minimum: 1   Multiples: 1
Unit Price:
$-.--
Ext. Price:
$-.--
Est. Tariff:

Pricing (SGD)

Qty. Unit Price
Ext. Price
$59.70 $59.70
$48.71 $487.10
$45.95 $1,148.75
$42.94 $4,294.00
$41.26 $10,397.52
2,520 Quote

Product Attribute Attribute Value Select Attribute
Texas Instruments
Product Category: Digital Signal Processors & Controllers - DSP, DSC
RoHS:  
DSPs
C55x
1 Core
160 MHz
BGA-240
352 kB
256 kB
24 kB
1.6 V
TMS320VC5510A
SMD/SMT
- 40 C
+ 85 C
Tray
Brand: Texas Instruments
Data ROM Size: 32 kB
I/O Voltage: 3.3 V
Instruction Type: Fixed Point
Moisture Sensitive: Yes
Number of Timers/Counters: 2 Timer
Product Type: DSP - Digital Signal Processors & Controllers
Factory Pack Quantity: 126
Subcategory: Embedded Processors & Controllers
Supply Voltage - Max: 1.65 V
Supply Voltage - Min: 1.55 V
Watchdog Timers: No Watchdog Timer
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CNHTS:
8542319090
USHTS:
8542310035
TARIC:
8542319000
ECCN:
3A991.a.2

Processors

Texas Instruments Processors provide a comprehensive portfolio, proven software, and worldwide support, enabling industry-leading automotive and industrial solutions. TI is dedicated to advancing and optimizing today’s processors to meet tomorrow’s intelligence, performance, and cost requirements in automotive and industrial applications. Scalable hardware and software platforms with common code allow designers to seamlessly reuse and migrate across devices to protect future investment.

TMS320VC5510A Fixed-Point DSPs

Texas Instruments TMS320VC5510A Fixed-Point Digital Signal Processors are based on the TMS320C55x DSP generation CPU processor core. These devices feature a C55x™DSP architecture that achieves high performance and low power through increased parallelism and a total focus on reducing power dissipation. The CPU supports an internal bus structure that includes one program bus, three data read buses, two data write buses and additional buses dedicated to peripheral and DMA activity. These buses can perform up to three data reads, and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.