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CD74AC164PWR

Name: Texas Instruments CD74AC164PWR
Brand: Texas Instruments
SKU: 595-CD74AC164PWR
Price: 2.11 SGD
Availability: InStock

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Mouser No:

595-CD74AC164PWR

Mfr. No:

CD74AC164PWR

Mfr.:

Texas Instruments

Description:

Counter Shift Registers 8-Bit Serial-In/Para llel-Out Shift Regis

Lifecycle:

New Product:

New from this manufacturer.

Datasheet:

CD74AC164PWR Datasheet

ECAD Model:

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More Information

Learn more about Texas Instruments CD74AC164PWR

In Stock: 2,925

Stock:: 2,925 Can Dispatch Immediately

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Factory Lead Time:: 12 Weeks Estimated factory production time for quantities greater than shown.

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Ext. Price:

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Pricing (SGD)

Qty.	Unit Price	Ext. Price
	$2.11	$2.11
	$1.29	$12.90
	$1.09	$27.25
	$0.823	$82.30
	$0.712	$178.00
	$0.624	$312.00
	$0.562	$562.00
Full Reel (Order in multiples of 3000)
	$0.481	$1,443.00
	$0.418	$2,508.00

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Product Attribute	Attribute Value	Select Attribute
Manufacturer:	Texas Instruments
Product Category:	Counter Shift Registers
RoHS:
Counter Type:	Serial-In, Parallel-Out
Counting Sequence:	Serial to Parallel
Number of Circuits:	8 Circuit
Number of Bits:	8 bit
Package/Case:	TSSOP-14
Logic Family:	AC
Logic Type:	Shift Register
Number of Input Lines:	4 Input
Output Type:	Push-Pull
Propagation Delay Time:	6 ns
Supply Voltage - Min:	1.5 V
Supply Voltage - Max:	5.5 V
Minimum Operating Temperature:	- 55 C
Maximum Operating Temperature:	+ 125 C
Packaging:	Reel
Packaging:	Cut Tape
Brand:	Texas Instruments
High Level Output Current:	- 24 mA
Input Type:	CMOS
Low Level Output Current:	24 mA
Mounting Style:	SMD/SMT
Number of Output Lines:	8 Output
Operating Supply Voltage:	1.5 V to 5.5 V
Product:	Shift Registers
Product Type:	Counter Shift Registers
Reset Type:	Asynchronous
Series:	CD74AC164
Factory Pack Quantity:	3000
Subcategory:	Logic ICs
Triggering Type:	Rising Edge

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Datasheet

CD74AC164PWR Datasheet

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CNHTS:: 8542399000
USHTS:: 8542390090
TARIC:: 8542319000
MXHTS:: 8542399999
ECCN:: EAR99

CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers

Texas Instruments CD74AC164/CD74ACT164 8-Bit SIPO Shift Registers have two serial inputs (A and B) connected through an AND gate and an asynchronous clear (CLR). The device requires a high signal on both A and B to set the input data line high; a low signal on either will set the input data line low. Data at A and B can be changed while CLK is high or low, provided the minimum set-up time requirements are met.